Art of Silicon

At Art of Silicon we have drawn on our experience to create a portfolio of multimedia IP.

All of our IP is created in line with the Reuse Methodology Manual, and delivered fully verified and documented with a reference model and testsuite.

IP cores

All of our IP Cores are available as Verilog or VHDL RTL ready for ASIC synthesis, or as an EDIF Netlist targetting Lattice, Xilinx or Altera FPGAs.

We can interface to any system bus through one of our bus interface blocks.

If you don't see what you require here, contact us about becoming a development partner for our future IP cores.

JPEG cores

JPEG Decoder

1 colour component decoder datasheet

JPEG Encoder

1 colour component encoder datasheet

Coming Soon

MPEG2 Cores

JPEG2000 Cores